Pipelining in microprocessor pdf

Microprocessors operate on numbers and symbols represented in the binary numeral system. The integration of a whole CPU onto a single chip or on a few chips greatly reduced the cost of processing power. The integrated circuit processor was produced in large numbers by highly automated processes, so unit cost was low. Single-chip processors increase reliability as there are many fewer electrical connections to fail. As microprocessor designs get faster, the cost of manufacturing a chip with smaller components built on a semiconductor chip the same size generally stays the same.

Before microprocessors, small computers had been implemented using racks of circuit boards with many medium- and small-scale integrated circuits. Microprocessors integrated this into one or a few large-scale ICs. Continued increases in microprocessor capacity have since rendered other forms of computers almost completely obsolete, with one or more microprocessors used in everything from the smallest embedded systems and handheld devices to the largest mainframes and supercomputers.

As integrated circuit technology advanced, it was feasible to manufacture more and more complex processors on a single chip. Additional features were added to the processor architecture; more on-chip registers sped up programs, and complex instructions could be used to make more compact programs.

Floating-point arithmetic, for example, was often not available on 8-bit microprocessors, but had to be carried out in software. Integration of the floating point unit first as a separate integrated circuit and then as part of the same microprocessor chip, sped up floating point calculations. History of few Was 10 times faster than Microprocessors : Could execute 5,00, : instructions per second Introduced in Its clock speed was 3 MHz.

Its clock speed was KHz. Its data bus is 8-bit and address It had 2, transistors. It could execute around 60, It had 6, transistors. Could execute 7,69, : Almost similar to , instructions per second. It could access 64 KB of memory.

Introduced in Over million copies were sold. Its clock speed is 4. Its data bus is bit and address bus is bit. Its clock speed was 2 MHz. It had 29, transistors. It had 6, transistors. Due to the 1Mbytes memory size multiprogramming is made feasible as well as several multiprogramming features have been incorporated in design.

Clock is generated by separate peripheral chip This is achieved by a concept called pipelining. The architecture is shown below. Instruction Queue 1. To increase the execution speed, BIU fetches as many as six instruction bytes ahead to time from memory. All six bytes are then held in first in first out 6 byte register called instruction queue.

Then all bytes have to be given to EU one by one. This pre fetching operation of BIU may be in parallel with execution operation of EU, which improves the speed execution of the instruction. The EU contains the control circuitry to perform various internal operations. A decoder in EU decodes the instruction fetched memory to generate different internal or external control signals required to perform the operation. EU has bit ALU, which can perform arithmetic and logical operations on 8-bit as well as bit.

AX Register: AX register is also known as accumulator register that stores operands for arithmetic operation like divided, rotate. BX Register: This register is mainly used as a base register. It holds the starting base location of a memory region within a data segment.

CX Register: It is defined as a counter. It is primarily used in loop instruction to store loop counter. Segment Registers Additional registers called segment registers generate memory address when combined with other in the microprocessor. In microprocessor, memory is divided into 4 segments as follow: 1.

Data are accessed in the Data Segment by an offset address or the content of other register that holds the offset address.

Extra Segment ES : ES is additional data segment that is used by some of the string to hold the destination data. Flag Registers of Flag register in EU is of bit and is shown in below fig : Flags Register determines the current state of the processor.

Remember, though, that the first instruction is just one step ahead of the second, so the contents of r1 and r2 are being added, but the result has not yet been written into register r3.

The second instruction therefore cannot read from the register r3 because it hasn't been written yet and must wait until the data it needs is stored. Consequently, the pipeline is stalled and a number of empty instructions known as bubbles go into the pipeline. Data dependency affects long pipelines more than shorter ones since it takes a longer period of time for an instruction to reach the final register-writing stage of a long pipeline.

MIPS' solution to this problem is code reordering. If, as in the example above, the following instructions have nothing to do with the first two, the code could be rearranged so that those instructions are executed in between the two dependent instructions and the pipeline could flow efficiently. The task of code reordering is generally left to the compiler, which recognizes data dependencies and attempts to minimize performance stalls.

Branch instructions are those that tell the processor to make a decision about what the next instruction to be executed should be based on the results of another instruction. Branch instructions can be troublesome in a pipeline if a branch is conditional on the results of an instruction which has not yet finished its path through the pipeline. On the same time as the body of the car is being constructed, the first team is working on the engine of the next car As each stage takes 1 hour there is no waiting, so we can produce one car per hour.

All the stages start simultaneously If all the stages are balanced the time taken by each instruction is defined by: Time taken per. We assume that each instruction can be executed in 5 clock cycles.

These 5 clock cycles can be broken up as follows: Instruction. In reality this cannot be achieved because the ALU cannot do a Multiplication and Addition operation at the same time But if instruction execution stages are independent, we can see how they are overlapped. The instructions issued before the stall are allowed to be executed. Open navigation menu. Close suggestions Search Search. User Settings. Skip carousel. Carousel Previous. Carousel Next. What is Scribd?

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Difficulty Beginner Intermediate Advanced. Explore Documents. PipeLining in Microprocessors. Uploaded by Sajid Janjua. Document Information click to expand document information Description: This is a presentation on the topic of pipelining in Microprocessors. It includes pipelining characteristics, implementing risc instruction set, 5 risc cycles and pipelining hazard.

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